1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more particularly, to a semiconductor device that includes a vertical MOSFET with a trench gate and a method of manufacturing the semiconductor device.
2. Description of the Related Art
As one of related-art vertical MOSFETs, the following vertical MOSFET is proposed, which is disclosed in, for example, Japanese Patent No. 5118270. Specifically, a gate electrode is formed only in the lower part of a trench formed in a substrate, and the upper part of the trench is filled with an interlayer insulating film for insulating a source electrode and the gate electrode from each other, so that the upper surface of the interlayer insulating film is substantially coplanar with the surface of the substrate. The source electrode is formed on the upper surface of the interlayer insulating film and the surface of the substrate. This configuration eliminates a contact opening for connecting a source electrode formed on an interlayer insulating film to a source region and a base contact region of the surface of a substrate, which is necessary in a case in which a gate electrode is filled up to the upper part of a trench, and an interlayer insulating film is formed on the surface of a substrate. As a result, the device can be downsized in its lateral direction.
In addition, in Japanese Patent No. 5118270 (see, in particular, FIG. 4A, FIG. 4B, and FIG. 5), there is a disclosure that the source regions and base contact regions are alternatively arranged in the surface of the substrate along the trenches disposed in a stripe pattern so that an interval between the adjacent trenches is reduced, with the result that the device can be further downsized.
However, in the related-art vertical MOSFET, which is proposed in, for example, Japanese Patent No. 5118270, in order to connect the source electrode to the source region and the base contact region, the source region and the base contact region are required to be arranged in the surface of the substrate in the lateral direction. The source region and the base contact region are accordingly required to be arranged with a certain margin in the lateral direction in consideration of the variation in manufacture. It is therefore difficult to still further downsize the device.
Further, in the structure in which the source regions and the base contact regions are alternatively arranged in the surface of the substrate along the trenches disposed in the stripe pattern, which is also disclosed in Japanese Patent No. 5118270, it is necessary to form the base contact regions in the surface of the substrate while reducing the area of the source regions necessary for channel formation. No channel is formed in the regions in which the base contact regions are formed, which results in a low channel density.